The present disclosure relates to devices including field programmable gate arrays. A field programmable gate array (FPGA) is an integrated circuit that can be configured after manufacturing. It is a flexible device having a great number of potential configuration modes to interact with various other hardware and software designs (e.g., on a computer motherboard). The FPGA configuration is generally specified using a hardware description language, similar to that used for an application specific integrated circuit (ASIC). Generally speaking, an FPGA can be configured to implement most or all logic functions that an ASIC could execute, yet also can be at least partially reconfigured after shipping. Coupled with relatively low design costs typically associated with ASIC design, FPGAs offer significant advantages for a wide array of electronic devices and applications.
The FPGA architecture generally comprises a set of programmable logic components, or logic blocks, and reconfigurable interconnects for selectively connecting a subset of the logic blocks with other subsets thereof. Logic blocks can be configured to execute complex algorithms, or simple logic functions like AND, NAND, NOR, etc. Most FPGAs also include memory elements that can include flip-flops, memory registers, memory arrays, or the like.
Like most integrated circuits, design goals for the FPGA include reducing minimum component size, increasing calculation speed, lowering power consumption, and others. As more applications are found for these devices, demand for improved technology comes from many sectors. Although FPGAs were largely used exclusively in telecommunications and networking in early implementations, their versatility has found these devices implemented in other industries, consumer, automotive and industrial applications.
One recent development of the general FGPA architecture was to combine embedded microprocessors with the traditional logic blocks and interconnects of the FPGA. This development has lead to what are referred to as system-on-chip or system on programmable chip devices. Many examples of system-on-chip devices have emerged, generally combining processor and analog peripheral components with the FPGA architecture. The system-on-chip has enabled the miniaturization of microprocessors to achieve a new paradigm. However, as is typical with electronics technology, new paradigms very rapidly lead to applications requiring smaller, faster or lower power devices, generating new demand for research and development.
A recent innovation for integrated circuit technology has been the concept of a resistive random access memory (RRAM). In theory, RRAM is a two-terminal, non-volatile memory technology that induces a filament (or many filaments) in a dielectric material. In a normal state, the dielectric has high resistance, and is non-conductive. However, application of a suitable voltage across the dielectric can induce a conduction path therein. Various physical mechanisms enable generation of a conduction path in a dielectric, including defects in the material (whether natural or induced via doping), metal migration, and so on. Once the filament is formed within the dielectric, it can be activated—resulting in a low resistance conduction path through the dielectric—or deactivated—rendering the dielectric a high resistance electrical insulator —through application of a suitable program or erase voltage, respectively. Thus, the conduction path can be referred to as a programmable conduction path, yielding similar electric characteristics as a conventional three-terminal transistor. In practice, however, the inventors of the present invention believe that the RRAM has not been commercially successful for reasons including incompatibility of RRAM fabrication materials with traditional CMOS processes, the incompatibility of RRAM processes as part of back end CMOS fabrication, and the like.
The inventors of the present invention believe that a basic memory cell architecture employing the RRAM technology could be a configuration of parallel bitlines intersected by perpendicular wordlines. A programmable resistance dielectric can be formed at the junction of each bitline and wordline. Such a basic memory cell would be referred to as a cross-point cell. One application of the RRAM cross-point cell, for instance, would be a block of reconfigurable interconnects within a FPGA. The RRAM cross-point cell may utilize RRAM memory cells of much smaller area than the comparable static random access memory (SRAM) counterpart. This reduction in area may lead to much greater component density. The RRAM cell also would have significantly lower power consumption, would be non-volatile memory (compared with volatile SRAM), radiation immune, would have quicker power-up, as well as other benefits. However, the inventors envision that the basic cross-point cell design may have large parasitic currents in non-activated memory cells, which may lead to slow read access. Moreover, the ratio of resistance in activated and deactivated states may not often be high enough for many sensitive applications, which might require such a ratio of 106 or greater. Thus, the inventors believe that utilizing RRAM memory cells in conjunction with the FPGA technology may provide some benefits, additional improvements in particular areas will help to make the RRAM cross-point cell suitable for a wider range of applications.